Verfahren zur Herstellung epitaxialer Schichten bestimmter Form

1,161,343. Semi-conductor devices. TEXAS INSTRUMENTS Inc. 17 Oct., 1966 [24 Oct., 1965], No. 46250/66. Heading H1K. In the manufacture of a semi-conductor device a semi-conductor wafer is provided with an apertured mask, holes are etched into the wafer through the mask with side walls parallel to slower or faster growth rate crystallographic planes than the bases of the holes and semiconductor deposited on the faster growth planes. If the substrate is semi-insulating it isolates the material grown in the pockets. Growth may occur primarily either from the base or from the sides of the pockets depending on the crystallographic orientation. Where the substrate is of N- or P-type isolation of the material in the pockets may be achieved by depositing or growing oxide insulation on the bases of the pockets and possibly on part of the side walls thereof and then growing material of the same conductivity type on the exposed parts of the pocket walls to bury the oxide. Isolation of the grown material is completed before or after device configurations are formed in the pockets by converting the grown material lining the parts of the pocket side walls exposed during the epitaxial growth to the opposite conductivity type by diffusion, or by etching away this material. Alternatively, isolation is achieved by arranging that the first grown material is of opposite conductivity type to the substrate, or by filling the pockets with such material and then converting the central portions to the same type as the substrate by diffusion. In another embodiment, in which the pocket and substrate materials are of opposite conductivity types the intervening PN junction is relied on for lateral isolation. Transistor and resistor configurations are formed in adjacent pockets by diffusion and interconnected to form a logic circuit (Fig. 15, not shown) by tracks formed on an oxide overlayer by vapour deposition overall followed by selective etching. Conventional photo-resist and etching techniques are used to fashion the masking and insulating layers from silicon oxide produced by thermal growth or by low temperature oxidation of tetraethoxysilane. Alternative insulating materials suggested are carbon-rich silicon carbide and alumina. Where silicon is deposited the technique of hydrogen reduction of silicon tetrachloride may be employed, in which case the reaction can be reversed to effect etching of the silicon substrate. It is stated that germanium gallium arsenide, gallium arsenoph