Zerstoerungsfrei auslesbare Speicherschaltung

975,952. Semi-conductor bi-stable circuits. KOGYOGIJUTSUIN-CHO. Jan. 27, 1961 [Jan. 28, 1960; March 7, 1960; Sept. 10, 1960], No. 3204/61. Heading H3T. A negative resistance diode memory circuit is readout by switching a diode into its negative resistance region and detecting the oscillations produced. In a first embodiment, Fig. 4, if tunnel diode 4 is in its high voltage state, the application of a short duration negative read pulse will switch it into its negative resistance region and the circuit will oscillate at a frequency determined by inductor 3 and capacitor 17, the oscillation being fed by way of waveguide 18 to a detector 19. If the diode is in its low voltage state no oscillation occurs. Alternatively, positive read pulses may be applied to produce oscillation in the low voltage state. The read pulses may be applied through an AND circuit comprising resistors 20, 21. In a modification, Fig. 11 (not shown), the tuned circuit comprises the self capacitance of the inductor. In a second embodiment, Fig. 8, the tunnel diode 4 is biased to have one non- oscillatory state, and one oscillatory state. Readout is effected by applying pulses to terminals 32, 33 to switch tunnel diode 41 to its low resistance state, thus coupling the oscillations into the waveguide. In a third embodiment, Fig. 14, tunnel diode 4 has two stable states in one of which the potential across it, together with a read pulse at terminals 32, 33 is sufficient to switch tunnel diode 41 into its negative resistance region, and produce oscillations. The circuits may be employed in matrix memory units.