Mit Pulscodemodulation arbeitende UEber-tragungsanordnung

947,430. Pulse code modulation systems. A. E. PINET, and G. BATTAIL. Oct. 27, 1961 [Nov. 30, 1960], No. 38534/61. Heading H4L. In a pulse code modulation system of the type in which signal samples are first converted into duration modulated pulses and pulses from a pulse generator are counted for the duration of each modulated pulse, the resulting count being translated into binary form for transmission, the frequency of the pulse generator is varied in steps by arranging for it to be halved at predetermined amplitudes of the modulating signal to provide amplitude compression. Decoding arrangements in which the converse occurs are also described. As shown in Fig. 3, signal samples are supplied via terminals 101 to a sign detector 102 controlling a flip-flop 56. The signal from 101 is also supplied via a gate 104 to a pulse duration modulator 106 or via an inverter 103 and gate 105 to the modulator 106, the gates 104, 105 being controlled by the flip-flop 56. A pulse generator 3 via a frequency control circuit 9 supplies pulses to an AND gate 4 which passes pulses to a binary counter 5 for the duration of the pulse from 106. The counter 5 comprises flip-flops 50 to 55 which at the completion of a count are set to represent the corresponding binary number, a pulse from a timing pulse generator 7 transferring corresponding code pulses via gates 60 to 65 to a tapped delay line 8 and thence in serial form to the output line 2. A further pulse from flipflop 56 via gate 66 represents the sign of the input signal. The circuit 9 consists of a binary chain 911, 912, 913 controlled by the counter 5 through AND gates 930 to 933 which can only be opened one at a time to produce amplitude compression as shown in Fig. 2. The arrangement is such that the pulse repetition frequency from generator 3 is divided by eight when the generator is connected to terminal 923, by four when it is connected to terminal 922, and by two when it is connected to terminal 921, no frequency division taking place when it is connected to terminal 920. AND gate 930 is arranged to be open up to the value 16 as indicated by the counter 5, AND gate 931 is then open up to the value 32, AND gate 932 up to the value 48 and AND gate 933 up to the value 63. In a modification, Fig. 8 (not shown), the frequency division of the pulse output of oscillator 3 is controlled by a matrix arrangement of gating circuits selectively responsive to the particular binary combinations (the transition codes) at which t