Verfahren und Einrichtung zum Betrieb einer Schaltung mit zwei oder mehreren magnetisierbaren Elementen
874,944. Circuits employing bi-stable magnetic elements. RADIO CORPORATION OF AMERICA. Nov. 1, 1957 [Dec. 31, 1956 (2)], No. 34236/57. Class 40 (9). [Also in Group XIX] Spaced pulses of intense amplitude and short duration are applied to a core formed of rectangular hysteresis loop material, each pu...
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Zusammenfassung: | 874,944. Circuits employing bi-stable magnetic elements. RADIO CORPORATION OF AMERICA. Nov. 1, 1957 [Dec. 31, 1956 (2)], No. 34236/57. Class 40 (9). [Also in Group XIX] Spaced pulses of intense amplitude and short duration are applied to a core formed of rectangular hysteresis loop material, each pulse producing a magnetizing force which is considerably in excess of the coercive force of the core material, and having a duration which is sufficiently short as to cause a momentary variation of the core flux without effecting any significant permanent change of the remanent magnetism. In an amplifying and gating arrangement, Fig. 4, short duration and intense amplitude pulses are applied from a drive source 44 to windings 51, 52 on a pair of cores 40, 42. When the core 42 is magnetized to a state N by D.C. energization of a set winding 48, the short-duration pulses each produce a momentary flux excursion towards state P and a large output pulse comprising positive and negative halves is induced in a winding 54. Output pulse generation is terminated by D.C. energization of a reset winding 50 which reverses the core magnetization to state P, and flux excursions in the saturated region due to the short-duration pulses generate only small output pulses in winding 42. The output is applied to a load 46 by way of a kicking winding 53 on core 40 and a rectifying and smoothing circuit 80, 86, the core 40 being magnetized in the P state by a reset winding (not shown) so as to suppress the small output pulses in the load circuit. The short-duration, pulses may also be utilized in a co-ordinate memory array, Fig. 6, comprising storage cores 100 and row and column windings 110, 116. In operation, coded signals representing two binary digits of order 2 and 21 are applied to a crystal diode decoder 102 the four-way output of which selectively enables one of four separate row driver gates in a word-selection switch 104. A pulse from an interrogation source 106 or a read-write source 108 is then able to pass to a selected row winding. Information stored in the memory is read out by applying a positive read pulse 124 to the desired row of cores through the selection switch 104, and the resultant output signals generated in the column windings by driving all the row cores to state P are applied to sensing amplifiers S1-S8. This phase is followed by a writing operation in which a negative pulse 120 is applied over the selection switch to a desired row, while a positive inhibit |
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