Prozessorarchitektur mit einem Array von Pipelines und einer Registerdatei zum Vermeiden von Datenrisiken und Verfahren zur Datenweiterleitung in einer derartigen Prozessorarchitektur

Method for data transmission in a processor architecture (200) of the type having an array of pipelines (210) and a register file (202). Method involves shifting of speculative data from the pipelines to first registers of the register file, reading of the speculative data from the first registers a...

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Bibliographische Detailangaben
Hauptverfasser: FETZER, ERIC S, SOLTIS, DONALD C, UNDY, STEPHEN R
Format: Patent
Sprache:ger
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Zusammenfassung:Method for data transmission in a processor architecture (200) of the type having an array of pipelines (210) and a register file (202). Method involves shifting of speculative data from the pipelines to first registers of the register file, reading of the speculative data from the first registers and further transmission of the speculative data to the pipelines. The inventive method reduces the risk of data loss or corruption. An Independent claim is made for a processor architecture for circumventing data risks. Said processor comprises a pipeline array, register file and a read multiplexer (204) for coupling the two together.