Halbleiterspeicher mit vertikalen Charge-trapping-Speicherzellen und Verfahren zu seiner Herstellung

On surface of semiconductor substrate are located numerous, parallel spaced troughs (7,8). On the surface is located memory cell field (10) with memory transistors wall-fitted channel region separated from gate electrode by gate dielectric. The troughs consist of alternative insulation (7) and active troughs (8), with insulation troughs also located between lower bit lines. Bit line contacts (16,17) are fitted on top bit lines (15) and other bit line contacts (17) are fitted on lower bit lines, coupled conductively to metallising plane for wiring. The contacts are fitted on opposite sides of memory cell field. Independent claims are included for method of manufacturing semiconductor ROM with vertical charge trapping memory cells.