Latenz-Zeitschalter für ein S-DRAM

The device produces a time-delayed data release signal and has a controllable latency time generator for time delay of a decoded external data release signal with an adjustable latency time. A comparison circuit compares a cycle time for the high frequency clock signal with a predefined signal transition time for the data path and reduces the latency time generator latency time by the cycle time if the signal transition time exceeds the cycle time. The device produces a time-delayed data release signal for time-synchronous data transfer via a S-DRAM data path and has a controllable latency time generator (57) for time delay of a decoded external data release signal with an adjustable latency time. A comparison circuit (60) compares a cycle time for the high frequency clock signal (CLK) with a predefined signal transition time for the data path and reduces latency time of the latency time generator by the cycle time if the signal transition time exceeds the cycle time.