ON-CHIP-AUSFÜHRUNG EINES IN-SYSTEM-TESTS UNTER VERWENDUNG EINES VERALLGEMEINERTEN TESTBILDES
Systeme und Verfahren ermöglichen das Aktualisieren von Tests, Testsequenzen, Fehlermodellen und Testbedingungen wie Spannung und Taktfrequenzen über den Lebenszyklus einer sicherheitskritischen Anwendung für komplexe integrierte Schaltungen und Systeme hinweg. Systems and methods enable the updatin...
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| creator | Nerallapally, Venkat Abilash Reddy Sarangi, Shantanu K Sonawane, Milind Bhaiyyasaheb Chadalavada, Sailendra Manesh, Rangavajjula Kameswara Naga Pandey, Jayesh Kumar Raj, Sumit |
| description | Systeme und Verfahren ermöglichen das Aktualisieren von Tests, Testsequenzen, Fehlermodellen und Testbedingungen wie Spannung und Taktfrequenzen über den Lebenszyklus einer sicherheitskritischen Anwendung für komplexe integrierte Schaltungen und Systeme hinweg.
Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_DE102020111259A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>DE102020111259A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_DE102020111259A13</originalsourceid><addsrcrecordid>eNrjZIj199N19vAM0HUMDXY7PMcjKNTPXcHV0881WMHTTzc4MjjE1Vc3xDU4JFgh1C_ENUghzDUo3NXPBaEMKODo4-Pu6gviBoW4-imAlDt5-ri4BvMwsKYl5hSn8kJpbgZVN9cQZw_d1IL8-NTigsTk1LzUkngXV0MDIyA0NDQ0MrV0NDQmVh0AYY81iw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ON-CHIP-AUSFÜHRUNG EINES IN-SYSTEM-TESTS UNTER VERWENDUNG EINES VERALLGEMEINERTEN TESTBILDES</title><source>esp@cenet</source><creator>Nerallapally, Venkat Abilash Reddy ; Sarangi, Shantanu K ; Sonawane, Milind Bhaiyyasaheb ; Chadalavada, Sailendra ; Manesh, Rangavajjula Kameswara Naga ; Pandey, Jayesh Kumar ; Raj, Sumit</creator><creatorcontrib>Nerallapally, Venkat Abilash Reddy ; Sarangi, Shantanu K ; Sonawane, Milind Bhaiyyasaheb ; Chadalavada, Sailendra ; Manesh, Rangavajjula Kameswara Naga ; Pandey, Jayesh Kumar ; Raj, Sumit</creatorcontrib><description>Systeme und Verfahren ermöglichen das Aktualisieren von Tests, Testsequenzen, Fehlermodellen und Testbedingungen wie Spannung und Taktfrequenzen über den Lebenszyklus einer sicherheitskritischen Anwendung für komplexe integrierte Schaltungen und Systeme hinweg.
Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.</description><language>ger</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201119&DB=EPODOC&CC=DE&NR=102020111259A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201119&DB=EPODOC&CC=DE&NR=102020111259A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Nerallapally, Venkat Abilash Reddy</creatorcontrib><creatorcontrib>Sarangi, Shantanu K</creatorcontrib><creatorcontrib>Sonawane, Milind Bhaiyyasaheb</creatorcontrib><creatorcontrib>Chadalavada, Sailendra</creatorcontrib><creatorcontrib>Manesh, Rangavajjula Kameswara Naga</creatorcontrib><creatorcontrib>Pandey, Jayesh Kumar</creatorcontrib><creatorcontrib>Raj, Sumit</creatorcontrib><title>ON-CHIP-AUSFÜHRUNG EINES IN-SYSTEM-TESTS UNTER VERWENDUNG EINES VERALLGEMEINERTEN TESTBILDES</title><description>Systeme und Verfahren ermöglichen das Aktualisieren von Tests, Testsequenzen, Fehlermodellen und Testbedingungen wie Spannung und Taktfrequenzen über den Lebenszyklus einer sicherheitskritischen Anwendung für komplexe integrierte Schaltungen und Systeme hinweg.
Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIj199N19vAM0HUMDXY7PMcjKNTPXcHV0881WMHTTzc4MjjE1Vc3xDU4JFgh1C_ENUghzDUo3NXPBaEMKODo4-Pu6gviBoW4-imAlDt5-ri4BvMwsKYl5hSn8kJpbgZVN9cQZw_d1IL8-NTigsTk1LzUkngXV0MDIyA0NDQ0MrV0NDQmVh0AYY81iw</recordid><startdate>20201119</startdate><enddate>20201119</enddate><creator>Nerallapally, Venkat Abilash Reddy</creator><creator>Sarangi, Shantanu K</creator><creator>Sonawane, Milind Bhaiyyasaheb</creator><creator>Chadalavada, Sailendra</creator><creator>Manesh, Rangavajjula Kameswara Naga</creator><creator>Pandey, Jayesh Kumar</creator><creator>Raj, Sumit</creator><scope>EVB</scope></search><sort><creationdate>20201119</creationdate><title>ON-CHIP-AUSFÜHRUNG EINES IN-SYSTEM-TESTS UNTER VERWENDUNG EINES VERALLGEMEINERTEN TESTBILDES</title><author>Nerallapally, Venkat Abilash Reddy ; Sarangi, Shantanu K ; Sonawane, Milind Bhaiyyasaheb ; Chadalavada, Sailendra ; Manesh, Rangavajjula Kameswara Naga ; Pandey, Jayesh Kumar ; Raj, Sumit</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_DE102020111259A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>ger</language><creationdate>2020</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>Nerallapally, Venkat Abilash Reddy</creatorcontrib><creatorcontrib>Sarangi, Shantanu K</creatorcontrib><creatorcontrib>Sonawane, Milind Bhaiyyasaheb</creatorcontrib><creatorcontrib>Chadalavada, Sailendra</creatorcontrib><creatorcontrib>Manesh, Rangavajjula Kameswara Naga</creatorcontrib><creatorcontrib>Pandey, Jayesh Kumar</creatorcontrib><creatorcontrib>Raj, Sumit</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nerallapally, Venkat Abilash Reddy</au><au>Sarangi, Shantanu K</au><au>Sonawane, Milind Bhaiyyasaheb</au><au>Chadalavada, Sailendra</au><au>Manesh, Rangavajjula Kameswara Naga</au><au>Pandey, Jayesh Kumar</au><au>Raj, Sumit</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ON-CHIP-AUSFÜHRUNG EINES IN-SYSTEM-TESTS UNTER VERWENDUNG EINES VERALLGEMEINERTEN TESTBILDES</title><date>2020-11-19</date><risdate>2020</risdate><abstract>Systeme und Verfahren ermöglichen das Aktualisieren von Tests, Testsequenzen, Fehlermodellen und Testbedingungen wie Spannung und Taktfrequenzen über den Lebenszyklus einer sicherheitskritischen Anwendung für komplexe integrierte Schaltungen und Systeme hinweg.
Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING |
| title | ON-CHIP-AUSFÜHRUNG EINES IN-SYSTEM-TESTS UNTER VERWENDUNG EINES VERALLGEMEINERTEN TESTBILDES |
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