Chip container used in production of electronic, especially optoelectronic, components has cavity plate provided with etched cavities for each semiconductor chip
A chip container (7) has a cavity plate (2) provided with etched cavities (8) for each semiconductor chip (9). An independent claim is also included for the production of a chip container. In einen Halbleiterwafer sind Kavitäten zum Aufbewahren von Halbleiterchips anisotrop geätzt. Mit einer Orienti...
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| creator | DACHS, JUERGEN SINGER, FRANK BACHLER, ALFRED KAEMPF, MATHIAS |
| description | A chip container (7) has a cavity plate (2) provided with etched cavities (8) for each semiconductor chip (9). An independent claim is also included for the production of a chip container.
In einen Halbleiterwafer sind Kavitäten zum Aufbewahren von Halbleiterchips anisotrop geätzt. Mit einer Orientierung des Wafers in (100)-Ziehrichtung ergeben sich geometrisch exakt geätzte Seitenwände der Kavitäten mit einem Winkel von 125,3 DEG . Dadurch wird erreicht, dass Chips mit geringer Gefahr der Beschädigung in die Kavität rutschen können. Auf der Kavitätenplatte befindet sich eine transparente Deckelplatte. |
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In einen Halbleiterwafer sind Kavitäten zum Aufbewahren von Halbleiterchips anisotrop geätzt. Mit einer Orientierung des Wafers in (100)-Ziehrichtung ergeben sich geometrisch exakt geätzte Seitenwände der Kavitäten mit einem Winkel von 125,3 DEG . Dadurch wird erreicht, dass Chips mit geringer Gefahr der Beschädigung in die Kavität rutschen können. Auf der Kavitätenplatte befindet sich eine transparente Deckelplatte.</description><edition>7</edition><language>eng ; ger</language><subject>ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR ; BASIC ELECTRIC ELEMENTS ; CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS,e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES,DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS ; CONVEYING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; HANDLING THIN OR FILAMENTARY MATERIAL ; PACKAGES ; PACKAGING ELEMENTS ; PACKING ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; STORING ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS ; TRANSPORTING</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20041125&DB=EPODOC&CC=DE&NR=102004014208A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20041125&DB=EPODOC&CC=DE&NR=102004014208A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DACHS, JUERGEN</creatorcontrib><creatorcontrib>SINGER, FRANK</creatorcontrib><creatorcontrib>BACHLER, ALFRED</creatorcontrib><creatorcontrib>KAEMPF, MATHIAS</creatorcontrib><title>Chip container used in production of electronic, especially optoelectronic, components has cavity plate provided with etched cavities for each semiconductor chip</title><description>A chip container (7) has a cavity plate (2) provided with etched cavities (8) for each semiconductor chip (9). An independent claim is also included for the production of a chip container.
In einen Halbleiterwafer sind Kavitäten zum Aufbewahren von Halbleiterchips anisotrop geätzt. Mit einer Orientierung des Wafers in (100)-Ziehrichtung ergeben sich geometrisch exakt geätzte Seitenwände der Kavitäten mit einem Winkel von 125,3 DEG . Dadurch wird erreicht, dass Chips mit geringer Gefahr der Beschädigung in die Kavität rutschen können. Auf der Kavitätenplatte befindet sich eine transparente Deckelplatte.</description><subject>ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS,e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES,DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS</subject><subject>CONVEYING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>HANDLING THIN OR FILAMENTARY MATERIAL</subject><subject>PACKAGES</subject><subject>PACKAGING ELEMENTS</subject><subject>PACKING</subject><subject>PERFORMING OPERATIONS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STORING</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjrEOwjAMRLswIOAfvLCBlBYGVgRFfAB7FbmuYinEUWOK-jn8KSliYGTyyXe6e_PidXIcASWo5UA9PBK1wAFiL-0DlSWAdECeUHsJjBugFAnZej-CRJVfC-UeJVDQBM4mQDuwjhC9VZoKB25z-ZPVASm6rD8JpgSd9EAWHSS6c6aZtvMLM9yymHXWJ1p976JYX-rb6bqlKE2GsUiBtDnXpamM2ZtyX5nDsdz9m3sD0BxX7w</recordid><startdate>20041125</startdate><enddate>20041125</enddate><creator>DACHS, JUERGEN</creator><creator>SINGER, FRANK</creator><creator>BACHLER, ALFRED</creator><creator>KAEMPF, MATHIAS</creator><scope>EVB</scope></search><sort><creationdate>20041125</creationdate><title>Chip container used in production of electronic, especially optoelectronic, components has cavity plate provided with etched cavities for each semiconductor chip</title><author>DACHS, JUERGEN ; SINGER, FRANK ; BACHLER, ALFRED ; KAEMPF, MATHIAS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_DE102004014208A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; ger</language><creationdate>2004</creationdate><topic>ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS,e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES,DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS</topic><topic>CONVEYING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>HANDLING THIN OR FILAMENTARY MATERIAL</topic><topic>PACKAGES</topic><topic>PACKAGING ELEMENTS</topic><topic>PACKING</topic><topic>PERFORMING OPERATIONS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STORING</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>DACHS, JUERGEN</creatorcontrib><creatorcontrib>SINGER, FRANK</creatorcontrib><creatorcontrib>BACHLER, ALFRED</creatorcontrib><creatorcontrib>KAEMPF, MATHIAS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DACHS, JUERGEN</au><au>SINGER, FRANK</au><au>BACHLER, ALFRED</au><au>KAEMPF, MATHIAS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Chip container used in production of electronic, especially optoelectronic, components has cavity plate provided with etched cavities for each semiconductor chip</title><date>2004-11-25</date><risdate>2004</risdate><abstract>A chip container (7) has a cavity plate (2) provided with etched cavities (8) for each semiconductor chip (9). An independent claim is also included for the production of a chip container.
In einen Halbleiterwafer sind Kavitäten zum Aufbewahren von Halbleiterchips anisotrop geätzt. Mit einer Orientierung des Wafers in (100)-Ziehrichtung ergeben sich geometrisch exakt geätzte Seitenwände der Kavitäten mit einem Winkel von 125,3 DEG . Dadurch wird erreicht, dass Chips mit geringer Gefahr der Beschädigung in die Kavität rutschen können. Auf der Kavitätenplatte befindet sich eine transparente Deckelplatte.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR BASIC ELECTRIC ELEMENTS CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS,e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES,DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS CONVEYING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS HANDLING THIN OR FILAMENTARY MATERIAL PACKAGES PACKAGING ELEMENTS PACKING PERFORMING OPERATIONS SEMICONDUCTOR DEVICES STORING TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS TRANSPORTING |
| title | Chip container used in production of electronic, especially optoelectronic, components has cavity plate provided with etched cavities for each semiconductor chip |
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