Verfahren zur Verifikation digitaler arithmetischer Schaltungen mittels eines Äquivalenzvergleiches

Method for verification of arithmetic digital circuits in which a first circuit, called the specification, is compared for equivalence with a second circuit, called the implementation. Equivalence is said to be obtained when the same input signals generate the same outputs. According to the method the gate description is converted into a network of elementary 1-bit operations (XOR, half-adder, full-adder). Equivalence of specification and implementation is achieved when network circuits for each yield the same results.