Circuit for optional creation of an output signal from one of several cycle/clock signals connects an input cycle/clock signal through to the output signal
Input cycle/clock signals (CLKSRC1-CLKSRCn) are available on a multiplexer (MUX), which routes one of these signals to its output by relying on an option signal (CFGi) at its control input. An output signal (MUXOUT) for the multiplexer is routed as an output signal (CLKOUT) via a switch (S) and a la...
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Sprache: | eng ; ger |
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