Semiconductor chip processing and testing device

The utility model discloses a semiconductor chip processing testing device, which comprises a testing mechanism and an adjusting mechanism, the adjusting mechanism is fixedly connected to the top of the testing mechanism, the adjusting mechanism comprises an adjusting box, the rear side of the right...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: KIMURA TAMOTSU
Format: Patent
Sprache:chi ; eng
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Beschreibung
Zusammenfassung:The utility model discloses a semiconductor chip processing testing device, which comprises a testing mechanism and an adjusting mechanism, the adjusting mechanism is fixedly connected to the top of the testing mechanism, the adjusting mechanism comprises an adjusting box, the rear side of the right side of the inner cavity of the adjusting box is fixedly connected with a motor, the output end of the motor is fixedly connected with a first gear, and the first gear is fixedly connected with a second gear. The front side of an inner cavity of the adjusting box is movably connected with a screw through a bearing, the right side of the surface of the screw is sleeved with a second gear, the back face of the second gear is meshed with the first gear, the left side of the surface of the screw is in threaded connection with a screw block, the top of the screw block is fixedly connected with a protruding plate, and the rear side of the top of the protruding plate is fixedly connected with a longitudinal block. Accord