Large capacitive load power-up buffer circuit
The utility model relates to the technical field of power-up buffer circuits, in particular to a large capacitive load power-up buffer circuit, which comprises a resistor R1, a resistor R2 and a resistor R3, one end of the resistor R1 is respectively connected with one end of the resistor R2, one en...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The utility model relates to the technical field of power-up buffer circuits, in particular to a large capacitive load power-up buffer circuit, which comprises a resistor R1, a resistor R2 and a resistor R3, one end of the resistor R1 is respectively connected with one end of the resistor R2, one end of the resistor R3, a voltage input end and a source electrode of a P-channel MOS (Metal Oxide Semiconductor) tube VT1, and the other end of the resistor R1 is connected with the source electrode of the P-channel MOS tube VT1. The other end of the resistor R1 is respectively connected with the other end of the resistor R2, the other end of the resistor R3, a drain electrode of a P-channel MOS tube VT1, one end of a resistor R7, one end of a capacitor C1 and a voltage output end, a grid electrode of the P-channel MOS tube VT1 is connected with a collector electrode of an NPN triode VT2, a base electrode of the NPN triode VT2 is connected with an anode of a voltage stabilizing diode D1, a cathode of the voltage sta |
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