Resistance network cell region and built-in self-tester of semiconductor device

The utility model relates to a resistive network cell region, a built-in self-tester, and a semiconductor device. A built-in self-tester (BIST) of a semiconductor device includes an input/output (I/O) circuit including an output buffer and an input buffer, an output terminal of the output buffer bei...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHEN BAITING, HONG CHONGLUN, LI SHAOYU, CHEN HUANNENG, CHEN CUNCUN
Format: Patent
Sprache:chi ; eng
Schlagworte:
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