Resistance network cell region and built-in self-tester of semiconductor device

The utility model relates to a resistive network cell region, a built-in self-tester, and a semiconductor device. A built-in self-tester (BIST) of a semiconductor device includes an input/output (I/O) circuit including an output buffer and an input buffer, an output terminal of the output buffer being coupled to an input terminal of the input buffer at an I/O terminal configured to receive or provide an external I/O signal; one or more resistive network cell regions arranged to influence a reference current received at the I/O terminals; and a switching device configured to selectively couple the one or more resistive network cell regions to a first reference voltage during a first phase or to a second reference voltage during a second phase in an alternating manner, the switching device is further configured to determine electrostatic discharge (ESD) damage to a metal oxide semiconductor (MOS) transistor included in the semiconductor device based on (1) the phase and (2) the output signal of the input buffer