Integrated chip and semiconductor structure

The utility model provides an integrated chip comprising an extending through hole and a semiconductor structure. The extending through hole spans the combined height of a wire and a through hole and has a smaller occupied area than the wire. The extended vias may replace the wires and adjacent vias at locations where the size and spacing of the wires reach a lower limit. Since the extended vias occupy less space than the lines, replacement of the conductive lines and adjacent vias with the extended vias may mitigate the spacing and allow further reduction in the size of the pixels. Extended vias may be applied to a capacitor array used in a pixel circuit. 本实用新型提供一种包括延伸通孔的集成芯片及半导体结构，所述延伸通孔跨越导线和通孔的组合高度且具有比导线更小的占地面积。延伸通孔可以在尺寸和导线的间隔达到下限的位置取代线和相邻的通孔。由于延伸通孔比线占用空间更小，因此用延伸通孔取代导线和相邻的通孔可以缓和间隔，并允许进一步减小像素的尺寸。延伸通孔可应用于像素电路中所用的电容器阵列。