Semiconductor packaging structure

The embodiment of the utility model relates to a semiconductor packaging structure. The semiconductor package structure includes a die having a front side and a back side; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on the front side of the die and electrically connected to the front side of the die; a through integrated fan-out via (TIV) disposed transverse to the die and extending to electrically connect the first and second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure; a plurality of pre-welding bumps; and a plurality of solder balls disposed on the second RDL structure and electrically connected to the second RDL structure. The enhancement layer includes a plurality of tandem openings electrically connected to the first RDL structure. Each of the pre-weld bumps is disposed in one of the concatenated openings. 本实用新型实施例涉及一种半导体封装结构。所述半导体封装