Heat sealing structure for chip packaging

The utility model relates to the technical field of chip packaging, in particular to a heat sealing structure for chip packaging, which comprises a first packaging layer. A mainboard is installed at the bottom end of the interior of the first packaging layer, a second packaging layer is clamped and...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	TAN AIJUN, LIU BING, DONG FENGZHI, SHANG JIANGUO, LIU YUEZU
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
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