Heat sealing structure for chip packaging

The utility model relates to the technical field of chip packaging, in particular to a heat sealing structure for chip packaging, which comprises a first packaging layer. A mainboard is installed at the bottom end of the interior of the first packaging layer, a second packaging layer is clamped and connected to the top end of the first packaging layer, a protection device is filled between the second packaging layer and the mainboard, a cavity for buffering pressure is formed in the protection device, the cavity is in an oval shape, and the protection device is connected with the mainboard. A plurality of electronic components are installed on the upper end face of the mainboard, through the arrangement of the first packaging layer, the second packaging layer, the arc groove, the mainboard, the protection device and the cavity, the bottom end of the protection device abuts against the mainboard placed on the inner edge face of the first packaging layer, the protection device is embedded through the second pac