ADSB-OUT emission time slot control chip based on FPGA

The utility model discloses a field programmable gate array (FPGA)-based ADSB-OUT emission time slot control chip, which is characterized in that internal resources of the FPGA are utilized to construct timers, triggers, a state device and an arbitration module, the seven different timers and triggers respectively carry out timing aiming at the emission period of one message, each timer carries out timing on the emission period of the message, and each timer carries out timing on the emission period of the message. The trigger sends a trigger signal to the state device when the transmitting period of the corresponding message is reached; the state device sequentially checks whether the triggers give trigger signals or not, obtains data of corresponding messages after receiving the trigger signals and sends the data to the transmitting queue; and the arbitration module arbitrates whether the seven messages can directly occupy the antenna according to the working state of the XPDR. According to the utility mode