Package structure

The utility model relates to a packaging structure. The packaging structure comprises a substrate; the first wiring layer is located on the substrate; the stacked chip set comprises a first chip and a second chip, and the first chip is located on the first wiring layer and connected with the first wiring layer; the second chip is stacked on the first chip; the packaging layer covers the first wiring layer, the first chip and the second chip; and the second wiring layer is positioned on the packaging layer and is connected with the second chip. According to the packaging structure, the first chip and the second chip in the stacked chip set are stacked, the first chip is connected with the first wiring layer, and the second chip is connected with the second wiring layer, so that the occupied area of the chips is reduced, and the integration level of the chips is improved. 本实用新型涉及一种封装结构，包括：衬底；第一走线层，位于衬底上；堆叠芯片组，包括第一芯片和第二芯片，第一芯片位于第一走线层上，且连接第一走线层；第二芯片堆叠设置于第一芯片上；封装层，覆盖第一走线层、第一芯片以及第二芯片；第二走线层，位于封装层上，且连接第二芯片。本实用新型的封装结构