Semiconductor structure

The utility model relates to a semiconductor structure, comprising a substrate having a first area, a second area surrounding the first area and a third area surrounding the second area; a device layer disposed on the substrate, a portion of the device layer above the first region including a device; a via layer disposed on the device layer, a first portion of the via layer above the first region including a first set of vias and a second portion of the via layer above the second region including a second set of vias; an interconnect structure disposed on the via layer, where a first portion of the interconnect structure over the first region includes conductive lines connected to the device, and a second portion of the interconnect structure over the second region includes a first set of dummy metal lines connected to a second set of vias, a third part of the interconnection structure on the third region comprises a second group of virtual metal lines; and a stress buffer layer having a wedge-shaped side pro