PMOS ideal diode circuit with adjustable conduction voltage drop
The utility model discloses a PMOS ideal diode circuit with adjustable conduction voltage drop. An ideal diode comprises an amplifier, a PMOS tube and a reference voltage source, the positive end of the ideal diode is P, and the negative end is N; the source electrode of the PMOS transistor is conne...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The utility model discloses a PMOS ideal diode circuit with adjustable conduction voltage drop. An ideal diode comprises an amplifier, a PMOS tube and a reference voltage source, the positive end of the ideal diode is P, and the negative end is N; the source electrode of the PMOS transistor is connected with the negative end N of the ideal diode, and the drain electrode is connected with the positive end P of the ideal diode; the positive phase input end INP of the amplifier is connected with the negative end N of the ideal diode, the negative phase input end INN of the amplifier is connected with the negative electrode of the reference voltage source, the output end OUT of the amplifier is connected with the grid electrode of the PMOS tube, the power supply is connected with VCC, and the ground is connected with GND; the anode of the reference voltage source is connected with the positive end P of the ideal diode. The circuit has the advantages that proper reference voltage is introduced, and the positive co |
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