Chip packaging structure for improving uniformity of bump and rewiring layer

The utility model provides a chip packaging structure capable of improving uniformity of bumps and a rewiring layer. The chip packaging structure comprises a wafer, the rewiring layer and the bumps, wherein the rewiring layer and the bumps are arranged on the surface of the wafer; the re-wiring layer comprises an actual re-wiring layer and a virtual re-wiring layer, the bumps comprise actual bumps and virtual bumps, the actual bumps are interconnected with the chip through the actual re-wiring layer, and the virtual bumps are in contact with the wafer through the virtual re-wiring layer; and arranging a rewiring layer and bumps on the invalid region of the wafer, wherein the height of the bumps in the invalid region is the same as that of the bumps in the effective region of the wafer. According to the utility model, the structures below the bumps are consistent, and virtual wiring is adopted for supporting at places without wiring, so that the height uniformity of the bumps is ensured structurally, and the r