Integrated circuit
The embodiment of the utility model relates to an integrated circuit. The utility model provides an integrated circuit. The integrated circuit comprises a semiconductor substrate; and a first semiconductor component including: a buried semiconductor region disposed in the semiconductor substrate and...
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| creator | BENOIT FROMENT CABOUT THOMAS |
| description | The embodiment of the utility model relates to an integrated circuit. The utility model provides an integrated circuit. The integrated circuit comprises a semiconductor substrate; and a first semiconductor component including: a buried semiconductor region disposed in the semiconductor substrate and having a first conductivity type; a first gate region and a second gate region disposed at a distance from each other and each extending in depth into the semiconductor substrate from the front surface of the semiconductor substrate, respectively, to the buried semiconductor region; a third gate region extending in depth into the semiconductor substrate from the front surface of the semiconductor substrate and configured to be electrically connected to the buried semiconductor region; and an active region of the semiconductor substrate defined by the first gate region, the second gate region, and the buried semiconductor region, the active region having a second conductivity type opposite the first conductivity ty |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN217182173UU</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN217182173UU</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN217182173UU3</originalsourceid><addsrcrecordid>eNrjZBDyzCtJTS9KLElNUUjOLEouzSzhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxzn5GhuaGFkDCODTUmChFAEluIOc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit</title><source>esp@cenet</source><creator>BENOIT FROMENT ; CABOUT THOMAS</creator><creatorcontrib>BENOIT FROMENT ; CABOUT THOMAS</creatorcontrib><description>The embodiment of the utility model relates to an integrated circuit. The utility model provides an integrated circuit. The integrated circuit comprises a semiconductor substrate; and a first semiconductor component including: a buried semiconductor region disposed in the semiconductor substrate and having a first conductivity type; a first gate region and a second gate region disposed at a distance from each other and each extending in depth into the semiconductor substrate from the front surface of the semiconductor substrate, respectively, to the buried semiconductor region; a third gate region extending in depth into the semiconductor substrate from the front surface of the semiconductor substrate and configured to be electrically connected to the buried semiconductor region; and an active region of the semiconductor substrate defined by the first gate region, the second gate region, and the buried semiconductor region, the active region having a second conductivity type opposite the first conductivity ty</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220812&DB=EPODOC&CC=CN&NR=217182173U$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220812&DB=EPODOC&CC=CN&NR=217182173U$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BENOIT FROMENT</creatorcontrib><creatorcontrib>CABOUT THOMAS</creatorcontrib><title>Integrated circuit</title><description>The embodiment of the utility model relates to an integrated circuit. The utility model provides an integrated circuit. The integrated circuit comprises a semiconductor substrate; and a first semiconductor component including: a buried semiconductor region disposed in the semiconductor substrate and having a first conductivity type; a first gate region and a second gate region disposed at a distance from each other and each extending in depth into the semiconductor substrate from the front surface of the semiconductor substrate, respectively, to the buried semiconductor region; a third gate region extending in depth into the semiconductor substrate from the front surface of the semiconductor substrate and configured to be electrically connected to the buried semiconductor region; and an active region of the semiconductor substrate defined by the first gate region, the second gate region, and the buried semiconductor region, the active region having a second conductivity type opposite the first conductivity ty</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBDyzCtJTS9KLElNUUjOLEouzSzhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxzn5GhuaGFkDCODTUmChFAEluIOc</recordid><startdate>20220812</startdate><enddate>20220812</enddate><creator>BENOIT FROMENT</creator><creator>CABOUT THOMAS</creator><scope>EVB</scope></search><sort><creationdate>20220812</creationdate><title>Integrated circuit</title><author>BENOIT FROMENT ; CABOUT THOMAS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN217182173UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BENOIT FROMENT</creatorcontrib><creatorcontrib>CABOUT THOMAS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BENOIT FROMENT</au><au>CABOUT THOMAS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit</title><date>2022-08-12</date><risdate>2022</risdate><abstract>The embodiment of the utility model relates to an integrated circuit. The utility model provides an integrated circuit. The integrated circuit comprises a semiconductor substrate; and a first semiconductor component including: a buried semiconductor region disposed in the semiconductor substrate and having a first conductivity type; a first gate region and a second gate region disposed at a distance from each other and each extending in depth into the semiconductor substrate from the front surface of the semiconductor substrate, respectively, to the buried semiconductor region; a third gate region extending in depth into the semiconductor substrate from the front surface of the semiconductor substrate and configured to be electrically connected to the buried semiconductor region; and an active region of the semiconductor substrate defined by the first gate region, the second gate region, and the buried semiconductor region, the active region having a second conductivity type opposite the first conductivity ty</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Integrated circuit |
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