High-sealing peer-to-peer flip-chip semiconductor lead frame

High-sealing peer-to-peer flip-chip semiconductor lead frame

The utility model discloses a high-sealing peer-to-peer flip-chip semiconductor lead frame, which comprises a main board, a plurality of rows of circular hole grooves are arranged in the main board, a plurality of groups of straight grooves are arranged in the main board, the plurality of groups of...

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Hauptverfasser: GU XIAOYING, CAO KAI, LI CHANGFENG, HUANG HAIHUA, CAO GANG, GU LIANGQING
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator GU XIAOYING
CAO KAI
LI CHANGFENG
HUANG HAIHUA
CAO GANG
GU LIANGQING
description The utility model discloses a high-sealing peer-to-peer flip-chip semiconductor lead frame, which comprises a main board, a plurality of rows of circular hole grooves are arranged in the main board, a plurality of groups of straight grooves are arranged in the main board, the plurality of groups of straight grooves and the circular hole grooves are arranged in a staggered manner, an upper sealing cover is arranged above the main board, and a lower sealing cover is arranged above the upper sealing cover. A chip penetrates through the middle of the upper sealing cover, pins are arranged at the bottom of the chip and connected with the mainboard in a tin soldering mode, a lower sealing cover is arranged below the mainboard, the lower sealing cover is welded to the upper sealing cover, a connecting plate is arranged on the upper surface of the mainboard, an inserting hole is formed in the connecting plate, and the inserting hole is connected with the upper sealing cover. The jacks are clamped with the straight gr
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN217114380UU</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN217114380UU</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN217114380UU3</originalsourceid><addsrcrecordid>eNrjZLDxyEzP0C1OTczJzEtXKEhNLdItydcF0QppOZkFuskZmQUKxam5mcn5eSmlySX5RQo5qYkpCmlFibmpPAysaYk5xam8UJqbQcnNNcTZQze1ID8-tbggMTk1L7Uk3tnPyNDc0NDE2MIgNNSYKEUAJrcwTg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>High-sealing peer-to-peer flip-chip semiconductor lead frame</title><source>esp@cenet</source><creator>GU XIAOYING ; CAO KAI ; LI CHANGFENG ; HUANG HAIHUA ; CAO GANG ; GU LIANGQING</creator><creatorcontrib>GU XIAOYING ; CAO KAI ; LI CHANGFENG ; HUANG HAIHUA ; CAO GANG ; GU LIANGQING</creatorcontrib><description>The utility model discloses a high-sealing peer-to-peer flip-chip semiconductor lead frame, which comprises a main board, a plurality of rows of circular hole grooves are arranged in the main board, a plurality of groups of straight grooves are arranged in the main board, the plurality of groups of straight grooves and the circular hole grooves are arranged in a staggered manner, an upper sealing cover is arranged above the main board, and a lower sealing cover is arranged above the upper sealing cover. A chip penetrates through the middle of the upper sealing cover, pins are arranged at the bottom of the chip and connected with the mainboard in a tin soldering mode, a lower sealing cover is arranged below the mainboard, the lower sealing cover is welded to the upper sealing cover, a connecting plate is arranged on the upper surface of the mainboard, an inserting hole is formed in the connecting plate, and the inserting hole is connected with the upper sealing cover. The jacks are clamped with the straight gr</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220802&amp;DB=EPODOC&amp;CC=CN&amp;NR=217114380U$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220802&amp;DB=EPODOC&amp;CC=CN&amp;NR=217114380U$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GU XIAOYING</creatorcontrib><creatorcontrib>CAO KAI</creatorcontrib><creatorcontrib>LI CHANGFENG</creatorcontrib><creatorcontrib>HUANG HAIHUA</creatorcontrib><creatorcontrib>CAO GANG</creatorcontrib><creatorcontrib>GU LIANGQING</creatorcontrib><title>High-sealing peer-to-peer flip-chip semiconductor lead frame</title><description>The utility model discloses a high-sealing peer-to-peer flip-chip semiconductor lead frame, which comprises a main board, a plurality of rows of circular hole grooves are arranged in the main board, a plurality of groups of straight grooves are arranged in the main board, the plurality of groups of straight grooves and the circular hole grooves are arranged in a staggered manner, an upper sealing cover is arranged above the main board, and a lower sealing cover is arranged above the upper sealing cover. A chip penetrates through the middle of the upper sealing cover, pins are arranged at the bottom of the chip and connected with the mainboard in a tin soldering mode, a lower sealing cover is arranged below the mainboard, the lower sealing cover is welded to the upper sealing cover, a connecting plate is arranged on the upper surface of the mainboard, an inserting hole is formed in the connecting plate, and the inserting hole is connected with the upper sealing cover. The jacks are clamped with the straight gr</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDxyEzP0C1OTczJzEtXKEhNLdItydcF0QppOZkFuskZmQUKxam5mcn5eSmlySX5RQo5qYkpCmlFibmpPAysaYk5xam8UJqbQcnNNcTZQze1ID8-tbggMTk1L7Uk3tnPyNDc0NDE2MIgNNSYKEUAJrcwTg</recordid><startdate>20220802</startdate><enddate>20220802</enddate><creator>GU XIAOYING</creator><creator>CAO KAI</creator><creator>LI CHANGFENG</creator><creator>HUANG HAIHUA</creator><creator>CAO GANG</creator><creator>GU LIANGQING</creator><scope>EVB</scope></search><sort><creationdate>20220802</creationdate><title>High-sealing peer-to-peer flip-chip semiconductor lead frame</title><author>GU XIAOYING ; CAO KAI ; LI CHANGFENG ; HUANG HAIHUA ; CAO GANG ; GU LIANGQING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN217114380UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GU XIAOYING</creatorcontrib><creatorcontrib>CAO KAI</creatorcontrib><creatorcontrib>LI CHANGFENG</creatorcontrib><creatorcontrib>HUANG HAIHUA</creatorcontrib><creatorcontrib>CAO GANG</creatorcontrib><creatorcontrib>GU LIANGQING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GU XIAOYING</au><au>CAO KAI</au><au>LI CHANGFENG</au><au>HUANG HAIHUA</au><au>CAO GANG</au><au>GU LIANGQING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>High-sealing peer-to-peer flip-chip semiconductor lead frame</title><date>2022-08-02</date><risdate>2022</risdate><abstract>The utility model discloses a high-sealing peer-to-peer flip-chip semiconductor lead frame, which comprises a main board, a plurality of rows of circular hole grooves are arranged in the main board, a plurality of groups of straight grooves are arranged in the main board, the plurality of groups of straight grooves and the circular hole grooves are arranged in a staggered manner, an upper sealing cover is arranged above the main board, and a lower sealing cover is arranged above the upper sealing cover. A chip penetrates through the middle of the upper sealing cover, pins are arranged at the bottom of the chip and connected with the mainboard in a tin soldering mode, a lower sealing cover is arranged below the mainboard, the lower sealing cover is welded to the upper sealing cover, a connecting plate is arranged on the upper surface of the mainboard, an inserting hole is formed in the connecting plate, and the inserting hole is connected with the upper sealing cover. The jacks are clamped with the straight gr</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title High-sealing peer-to-peer flip-chip semiconductor lead frame
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T15%3A15%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GU%20XIAOYING&rft.date=2022-08-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN217114380UU%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true