PNL-level packaging substrate

The utility model belongs to the technical field of chips, and provides a PNL-level packaging substrate, which comprises an ink layer, a metal layer and an insulating layer. Wherein the ink layer is positioned on the top layer of the substrate and is provided with a plurality of connecting positions, and the plurality of connecting positions are used for being correspondingly connected with single silicon wafers on a whole silicon wafer, so that the whole silicon wafer is connected with the ink layer; the metal layer is located below the ink layer and connected with the ink layer; the insulating layer is located below the metal layer and connected with the metal layer. Therefore, according to the PNL-level packaging substrate provided by the utility model, the overall transfer connection of the substrate and the silicon wafer can be realized, the efficiency of the transfer connection is improved, the difficulty of the transfer connection is reduced, the technical effect of mass transfer is realized, and the r