Efficient chip automatic test fixture

The utility model relates to the field of semiconductor test fixtures, in particular to an efficient chip automatic test fixture. Comprising a vacuum chuck, a groove is formed in the upper surface of the vacuum chuck, a plurality of adsorption tables are arranged in the groove, a chip to be tested is sleeved with the adsorption tables through chip limiting plates to limit the adsorption tables, a plurality of vacuum grooves are formed in the lower surface of the vacuum chuck and sealed through sealing plates to form a plurality of vacuum cavities, and a plurality of vacuum holes are formed in the side edge of the vacuum chuck. A plurality of vacuum holes and a plurality of vacuum cavities are formed in the upper surface and the lower surface of the vacuum suction cup respectively and independently communicated, a plurality of suction holes are formed in the upper portion and the lower portion of each suction table and communicated with the corresponding vacuum cavities, the suction tables on the upper surface