Test module of three-dimensional packaging chip
The utility model discloses a test module of a three-dimensional packaging chip, and relates to the technical field of printed circuit boards and three-dimensional packaging chips. Wherein the test module comprises a plurality of laminated plates which are sequentially stacked from top to bottom, an...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | The utility model discloses a test module of a three-dimensional packaging chip, and relates to the technical field of printed circuit boards and three-dimensional packaging chips. Wherein the test module comprises a plurality of laminated plates which are sequentially stacked from top to bottom, and a signal adapter plate which is arranged between every two adjacent laminated plates; at least onetest spot welding disc is arranged on each of the front and back surfaces of the laminated plate; the test spot welding discs on the front and back surfaces of the laminated plate are in short circuit in a one-to-one correspondence manner; the front face and the back face of the signal adapter plate are each provided with a signal adapter bonding pad, the signal adapter bonding pads on the frontface and the back face of the signal adapter plate are arranged in a one-to-one correspondence mode, and the signal adapter bonding pads on the front face and the back face correspondingly arranged onthe signal adapter plate a |
---|