Chip packaging structure and electronic equipment

The utility model discloses a chip packaging structure and electronic equipment, and belongs to the technical field of semiconductor chip packaging test. The chip packaging structure comprises a packaging substrate which is provided with a first surface and a second surface which are oppositely arranged; the at least one chip is arranged in the packaging substrate, the chip is provided with a third surface and a fourth surface which are oppositely arranged, and the third surface is provided with chip pins; and the heat dissipation structure is arranged in the packaging substrate and located onthe fourth surface of the chip, and the surface of the side, away from the chip, of the heat dissipation structure is exposed out of the second surface of the packaging substrate and used for providing a heat dissipation channel for the chip. According to the technical scheme of the utility model, the heat dissipation channels of the chip package can be increased, the heat dissipation capabilityof the chip package is eff