SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure

The utility model discloses an SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure. The utility model relates to the technical field of electronic chips. The metal lead frame is arranged in the epoxy resin plastic package; pins of the metal lead frame are exp...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LIU JIEFENG, WANG HAIQING, LIU WEIQIANG, CHEN ZELONG, XU GUIZHENG, LI ZHANGXIA
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator LIU JIEFENG
WANG HAIQING
LIU WEIQIANG
CHEN ZELONG
XU GUIZHENG
LI ZHANGXIA
description The utility model discloses an SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure. The utility model relates to the technical field of electronic chips. The metal lead frame is arranged in the epoxy resin plastic package; pins of the metal lead frame are exposed out of the epoxy resin plastic package, the first electrostatic protection chip and the third electrostatic protection chip are electrically connected and fixed to the upper side and the lower side of the upper surface of the bonding pad on the left side of the metal lead frame, and the secondelectrostatic protection chip is electrically connected and fixed to the bonding pad on the right side of the metal lead frame. The third electrostatic protection chip is electrically connected with the lower side of the upper surface of the metal lead frame located on the right side through a metal wire. The first electrostatic protection chip and the second electrostatic protection chip are electrically connected throug
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN210837744UU</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN210837744UU</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN210837744UU3</originalsourceid><addsrcrecordid>eNqNizEKwkAQANNYiPqHxT6gJhD7qFhpoemEsCxrbvG4O_Y25Pum8AFWw8DMsng97ifIrMIZnAyuTHFihdGboo9TSZiQxDAQA3sm05gNTQiSRptdYgBykmDuPjhIGCCbjmSj8rpYvNFn3vy4KraX87O9lpxiz3k-OLD17e2w3x2rpqnrrqv-ir6OpD2U</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure</title><source>esp@cenet</source><creator>LIU JIEFENG ; WANG HAIQING ; LIU WEIQIANG ; CHEN ZELONG ; XU GUIZHENG ; LI ZHANGXIA</creator><creatorcontrib>LIU JIEFENG ; WANG HAIQING ; LIU WEIQIANG ; CHEN ZELONG ; XU GUIZHENG ; LI ZHANGXIA</creatorcontrib><description>The utility model discloses an SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure. The utility model relates to the technical field of electronic chips. The metal lead frame is arranged in the epoxy resin plastic package; pins of the metal lead frame are exposed out of the epoxy resin plastic package, the first electrostatic protection chip and the third electrostatic protection chip are electrically connected and fixed to the upper side and the lower side of the upper surface of the bonding pad on the left side of the metal lead frame, and the secondelectrostatic protection chip is electrically connected and fixed to the bonding pad on the right side of the metal lead frame. The third electrostatic protection chip is electrically connected with the lower side of the upper surface of the metal lead frame located on the right side through a metal wire. The first electrostatic protection chip and the second electrostatic protection chip are electrically connected throug</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200623&amp;DB=EPODOC&amp;CC=CN&amp;NR=210837744U$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200623&amp;DB=EPODOC&amp;CC=CN&amp;NR=210837744U$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIU JIEFENG</creatorcontrib><creatorcontrib>WANG HAIQING</creatorcontrib><creatorcontrib>LIU WEIQIANG</creatorcontrib><creatorcontrib>CHEN ZELONG</creatorcontrib><creatorcontrib>XU GUIZHENG</creatorcontrib><creatorcontrib>LI ZHANGXIA</creatorcontrib><title>SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure</title><description>The utility model discloses an SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure. The utility model relates to the technical field of electronic chips. The metal lead frame is arranged in the epoxy resin plastic package; pins of the metal lead frame are exposed out of the epoxy resin plastic package, the first electrostatic protection chip and the third electrostatic protection chip are electrically connected and fixed to the upper side and the lower side of the upper surface of the bonding pad on the left side of the metal lead frame, and the secondelectrostatic protection chip is electrically connected and fixed to the bonding pad on the right side of the metal lead frame. The third electrostatic protection chip is electrically connected with the lower side of the upper surface of the metal lead frame located on the right side through a metal wire. The first electrostatic protection chip and the second electrostatic protection chip are electrically connected throug</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNizEKwkAQANNYiPqHxT6gJhD7qFhpoemEsCxrbvG4O_Y25Pum8AFWw8DMsng97ifIrMIZnAyuTHFihdGboo9TSZiQxDAQA3sm05gNTQiSRptdYgBykmDuPjhIGCCbjmSj8rpYvNFn3vy4KraX87O9lpxiz3k-OLD17e2w3x2rpqnrrqv-ir6OpD2U</recordid><startdate>20200623</startdate><enddate>20200623</enddate><creator>LIU JIEFENG</creator><creator>WANG HAIQING</creator><creator>LIU WEIQIANG</creator><creator>CHEN ZELONG</creator><creator>XU GUIZHENG</creator><creator>LI ZHANGXIA</creator><scope>EVB</scope></search><sort><creationdate>20200623</creationdate><title>SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure</title><author>LIU JIEFENG ; WANG HAIQING ; LIU WEIQIANG ; CHEN ZELONG ; XU GUIZHENG ; LI ZHANGXIA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN210837744UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LIU JIEFENG</creatorcontrib><creatorcontrib>WANG HAIQING</creatorcontrib><creatorcontrib>LIU WEIQIANG</creatorcontrib><creatorcontrib>CHEN ZELONG</creatorcontrib><creatorcontrib>XU GUIZHENG</creatorcontrib><creatorcontrib>LI ZHANGXIA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIU JIEFENG</au><au>WANG HAIQING</au><au>LIU WEIQIANG</au><au>CHEN ZELONG</au><au>XU GUIZHENG</au><au>LI ZHANGXIA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure</title><date>2020-06-23</date><risdate>2020</risdate><abstract>The utility model discloses an SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure. The utility model relates to the technical field of electronic chips. The metal lead frame is arranged in the epoxy resin plastic package; pins of the metal lead frame are exposed out of the epoxy resin plastic package, the first electrostatic protection chip and the third electrostatic protection chip are electrically connected and fixed to the upper side and the lower side of the upper surface of the bonding pad on the left side of the metal lead frame, and the secondelectrostatic protection chip is electrically connected and fixed to the bonding pad on the right side of the metal lead frame. The third electrostatic protection chip is electrically connected with the lower side of the upper surface of the metal lead frame located on the right side through a metal wire. The first electrostatic protection chip and the second electrostatic protection chip are electrically connected throug</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN210837744UU
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SOD series high-power ultralow-capacitance electrostatic protection chip packaging structure
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T17%3A24%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LIU%20JIEFENG&rft.date=2020-06-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN210837744UU%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true