Wide-voltage multi-channel digital IO system

The utility model relates to a wide-voltage multichannel digital IO system. The system comprises an FPGA circuit, a driving stage circuit, an external interface, a bus interface connected with the FPGA circuit, an SDRAM circuit, an hour hand circuit, a DSS circuit and a system power supply. Wherein the driving stage circuit is connected with a driving power supply connected with a logic power supply of a circuit board to be tested, and the driving stage circuit comprises a driving circuit, a comparison circuit and a reference generation circuit, wherein the driving circuit and the comparison circuit are connected with the FPGA circuit and an external interface, and the reference generation circuit is composed of two resistors and an operational amplifier. According to the utility model, the driving voltage of the driving stage circuit is directly connected with the logic power supply of the tested circuit, and the output logic level of the driving stage circuit is completely the same as the logic level of the