Three -dimensional semiconductor integrated morphology of bipolar monolithic

The utility model discloses a three -dimensional semiconductor integrated morphology of bipolar monolithic, it includes P type substrate, and light dope P type epitaxial layer is located P type substrate, and light dope N type epitaxial layer is located light dope P type epitaxial layer. Integrated between P type substrate and P type epitaxial layer have semiconductor device, and also the integration has semiconductor device on light dope N type epitaxial layer. The problem of prior art semiconductor unit / device of adopting the preparation of plane integrated technology within range, chip integration level that can only be present in near several microns to tens of microns in chip upper surface hang down is solved. With keeping apart by reverse bias's PN junction between the device of between the adjacent device in layer and different layers, the technology cost is lower. The interconnection is realized through the silicon through -hole between internal device and the surperficial device, interconnect struc