Plane high voltage MOS FET power transistor

The utility model provides a plane high voltage MOS FET power transistor, do you including N+ type substrate, be formed with N on N+ type substrate the type epitaxial layer, N type epitaxial layer upper portion is formed with the P type trap region of a plurality of cellulars, the doping concentration of P type trap region is by central authorities to both sides by dense to light, at N the most peripheral N+ type electric field cut -off ring that is formed with in front of type epitaxial layer, both sides respectively form N+ type source region in P type trap region, surface in P type trap region and N+ type source region top is formed with gate oxide, the last polycrystalline silicon layer that is formed with of gate oxide, be equipped with phosphorus silicon glass layer above polycrystalline silicon layer, be equipped with the source region metal in N+ type source region top phosphorus silicon glass layer uncovered region, does the source region metal level cover at N the type epitaxial layer openly to conn