Wafer level testing arrangement

The utility model discloses a wafer level testing arrangement, this testing arrangement includes: test lid, test seat and survey test panel, the test lid is used for testing the chip with WLCSP and impresses the test seat, with the inside test probes contact of test seat, test seat with survey the test panel contact, in order to pass through the test probes transmission survey signal to the WLCSPtest chip of exporting among the test panel, through the utility model discloses, can design a plurality of site on test seat and test, the space of having reduced testing arrangement has increased the productivity output. 本实用新型公开了种晶圆级测试装置，该测试装置包括：测试盖、测试座以及测试板，所述测试盖用于将WLCSP测试芯片压入所述测试座，与所述测试座内部的测试探针接触，所述测试座与所述测试板接触，以通过所述测试探针传输所述测试板中输出的信号到WLCSP测试芯片，通过本实用新型，可以在测试座上设计多个Site进行测试，减少了测试装置的空间，增加了产能产出。