High speed data admission memory system

The utility model discloses a high speed data admission memory system, including speed detect with speed difference circuit, speed difference and threshold value comparison circuit, memory regulationand control circuit, the speed detection is more electric with the threshold value with speed difference circuit connection speed difference, speed difference and threshold value comparison circuit connected storage regulation and control circuit, effectual present adoption bus technique, the parallel redundancy structure solved, efficiency, the reliability of guaranteeing high -speed data storageis brought hard masters, the costliness, is unfavorable for the problem of popularization and application. The utility model has the advantages of simple structure, according to current memory, the subtracter that is the core through operational amplifier AR1 carries out proportion subtraction with the high speed data transmission speed that detects with memory storage speed, it carries out subtraction with the magnitude