Chip packaging structure

The utility model discloses a chip packaging structure, this chip packaging structure includes the base plate, stack gradually in first chip, buffer layer and the second chip of base plate one side, wherein the buffer layer is in front outline on the base plate and the second chip is in front outlin...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	DONG HAORAN, XU MENGFENG, CHAO DAIYI
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!