Chip packaging structure

The utility model discloses a chip packaging structure, this chip packaging structure includes the base plate, stack gradually in first chip, buffer layer and the second chip of base plate one side, wherein the buffer layer is in front outline on the base plate and the second chip is in front outline on the base plate is located first chip is in in the front outline on the base plate, be located first chip is kept away from the power pad of a side surface of base plate, the power pad is in whole or partial being located of front outline on the base plate the second chip is in in the front outline on the base plate, the power pad pass through the wire directly or indirectly with base plate electrically connected, so that the base plate to the power supply of first chip. The embodiment of the utility model provides a technical scheme can realize reducing to encapsulate effects such as volume and expansion routing scope. 本实用新型公开了种芯片封装结构，该芯片封装结构包括基板，依次堆叠于所述基板侧的第芯片、缓冲层和第二芯片，其中所述缓冲层在所述基板上的垂直投影以及所述第二芯片在所述基板上的垂直投影位于所