Modified anticoincidence gate logic unit circuit

The utility model discloses a modified anticoincidence gate logic unit circuit constitutes first order circuit by PMOS transistor P1, P2 and NMOS transistor N1, N2, PMOS transistor P3, P4, P5 and NMOS transistor N3, N4, N5 constitute second level circuit. In the first order circuit, PMOS transistor...

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Bibliographische Detailangaben
Hauptverfasser:	LI WEI, SUN ZUAN, HU YINXIAO
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	The utility model discloses a modified anticoincidence gate logic unit circuit constitutes first order circuit by PMOS transistor P1, P2 and NMOS transistor N1, N2, PMOS transistor P3, P4, P5 and NMOS transistor N3, N4, N5 constitute second level circuit. In the first order circuit, PMOS transistor P1 and PMOS transistor P2 establish ties, and NMOS transistor N1 and NMOS transistor N2 are parallelly connected. In the circuit of the second level, PMOS transistor P3 and PMOS transistor P4 are parallelly connected, then establish ties with PMOS transistor P5, NMOS transistor N3 and NMOS transistor N4 establish ties, then parallelly connected with NMOS transistor N5. The utility model discloses the transistor quantity of using is 10, lacks 2 transistors than traditional anticoincidence gate logic unit circuit, has realized the exjunction logic having reduced the area through less transistor, has reduced the consumption.