Low stress wafer level image chip package structure

The utility model discloses a low stress wafer level image chip package structure, the fringe region all around of its image sensing chip lower surface distributes and has a plurality of blind hole, support the cofferdam and constitute by first support cofferdam layer and the second support cofferdam layer who stacks from top to bottom, this first support cofferdam layer and transparent cover contact, this second support cofferdam layer and image sensing chip contact, the second supports the cofferdam layer medial surface and has the V -arrangement breach that a plurality of was arranged in succession, four corners of the second supporting cofferdam layer are respectively provided with an arc -shaped gap. The blind hole is described the hole by the bowl and is constituteed with a straight hole that is located bowl form hole bottom portion, the upper shed in bowl form hole is 120~130 mu m in the blind hole, and the under shed is 62~68 mu m, and the bore depth is 40~45 microns. The utility model discloses the effectual process flow that shortens of ability, reduction in production cost reduces the structural stress, and has prevented that glue diffusion and reliability from increasing.