Transistor with multiple grid structure
The utility model discloses a transistor with multiple grid structure, include by the lower supreme substrate that stacks gradually, the buffer layer, the channel layer that gaN formed and the barrier layer of alGaN or inAlGaN formation, be provided with the source electrode on the barrier layer, dr...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | The utility model discloses a transistor with multiple grid structure, include by the lower supreme substrate that stacks gradually, the buffer layer, the channel layer that gaN formed and the barrier layer of alGaN or inAlGaN formation, be provided with the source electrode on the barrier layer, drain and be located a plurality of sub - grid between the two, this a little grid stands separately the interval by the source electrode to the drain electrode direction and arranges in order to form the multiple grid structure, each sub - grid includes the grid contact layer that is formed by p type al1 -xGaxN or p type in1 -y -zGayAlzN, 0 |
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