Double-end assembly line type copy bit line circuit

The utility model discloses a double-end assembly line type copy bit line circuit, wherein the specific realization thereof comprises two different realization modes according to different assembly times. The circuit is capable of reducing the process variation of a control time sequence generation circuit of a sensitive amplifier in an SRAM, thus reducing the process tolerance capacity of the control time sequence generation circuit of the sensitive amplifier in the SRAM, and the process variation can be reduced to a formula specified in the description in case of no influence on a bit line pre-charge time and no great increase for a design area; moreover, in order to ensure the equal average delay of the circuit disclosed by the utility model and the average delay of the traditional copy bit line circuit, then assembly times N is equal to M*K, and when M=1, namely, when the length of the copy bit line is equal to the length of the traditional copy bit line, the process variation of the obtained SAE is the minimum, and is 1/N of the variation of the SAE generated by the traditional copy bit line.