Clock domain-crossing asynchronous FIFO control logic circuit

The utility model discloses a clock domain-crossing asynchronous FIFO control logic circuit. The cross-clock domain asynchronous FIFO control logic circuit includes a read-write interface control circuit, an asynchronous FIFO chip and an output interface chip 54HC245, and the read-write interface co...

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Bibliographische Detailangaben
Hauptverfasser:	XU LI, WANG LIN, LUO XINGKE, CONG WEI, GENG PEITAO, HU JIALIN, ZHANG LIN
Format:	Patent
Sprache:	eng
Schlagworte:	CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING
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Beschreibung
Zusammenfassung:	The utility model discloses a clock domain-crossing asynchronous FIFO control logic circuit. The cross-clock domain asynchronous FIFO control logic circuit includes a read-write interface control circuit, an asynchronous FIFO chip and an output interface chip 54HC245, and the read-write interface control circuit includes a resistor R5, a resistor R6, a capacitor C33 and a capacitor C37. The read-write interface control circuit realizes control of read-write of an asynchronous signal, enables the asynchronous signal to adapt to working conditions of the asynchronous FIFO chip, the asynchronous FIFO chip overcomes metastable state interference, an output interface chip has an enhanced drive capability for an output signal of the FIFO chip, and internal noise interference is reduced. The circuit is simple in structure, strong in adaptability, low in cost, high in reliability, and low in power dissipation, overcomes a metastable state phenomenon, realizes transmission of clock domain-crossing parameters, and compared with a traditional asynchronous circuit, is faster in speed and lower in error rate.