Wafer acceptance test structure

The utility model discloses a wafer acceptance test structure. The wafer acceptance test structure is arranged in a slideway area of a wafer. The wafer acceptance test structure comprises a plurality of pads, wherein the total sum of the metal areas of the plurality of pads is less than or equal to one tenth of the total areas of the pads of the wafer acceptance test structure. According to the wafer acceptance test structure provided in the utility model, the metal areas of the pads are small, and dielectric substance is further reduced in an interconnection layer on the topmost layer, thereby reducing the energy of the laser during cutting the wafer, preventing generating too much heat, reducing the influence on device areas, and improving the reliability of final crystalline grains.