Active electric power filter based on FPGA phase lock control

The utility model relates to a filtering integrated device and particularly to a filter applied to electric power. The filter starts AD sampling of DSP by an obtained square wave signal with a sampling frequency, wherein the square wave signal is obtained via processing a square wave signal of a system voltage frequency in a frequency multiplication mode by FPGA. Meantime, DSP captures a square wave of a supply frequency via capturing (CAP) pins to obtain a zero crossing point during rising of a system voltage in a forward direction, and corrects a phase error of phase lock in real time when a phase angle is determined to be zero. DSP extracts a harmonic wave instruction utilizing a theory of instantaneous reactive power according to an acquired load current and a phase angle obtained by phase lock, and produces a current which has an equal value and an opposite direction compared with a load harmonic wave current utilizing a method of PI control, repetitive control and space vector, to make a current of a sy