Multiple input-multiple clock edge triggered D flip flop

The utility model discloses a multiple input-multiple clock edge triggered D flip flop which includes a multiple-input basic RS latch and at least two input units. The two input terminals of any input unit are connected with the input terminal of the multiple-input basic latch respectively to form an edge triggered D flip flop. The input unit includes a data input terminal and a clock triggering terminal. The multiple input-multiple clock edge triggered D flip flop can be used as a public memory, and is used for the design of a sequential circuit, and especially for the design of a distribution system driven by events and an asynchronous circuit. Compared with a conventional flip flop, the multiple input-multiple clock edge triggered D flip flop is driven directly by events under the multiple path data input condition. A data selection circuit is simple and the storage speed is rapid.