Thin film transistor array substrate

The utility model discloses a thin film transistor array substrate, which comprises a plurality of scanning lines which are parallel to one another, a plurality of data lines which intersect with the scanning lines in a vertical and insulating mode, pixel units which are defined by any two adjacent scanning lines and any two adjacent data lines and capacitance lines which are arranged between any two adjacent scanning lines. Long-shaped through holes are arranged on the capacitance lines along an extension direction of the capacitance lines, the long-shaped through holes are arranged on intersections between the capacitance lines and the data lines, and auxiliary capacitance lines which extend along an extension direction of the data lines are distributed symmetrically on two sides of the capacitance lines of hole walls of two sides of the long-shaped through holes. The thin film transistor array substrate can cut the connection between the auxiliary capacitance lines and the capacitance lines conveniently un