Multi-input and multi-clock maintenance obstruction type JK trigger
The present invention discloses a multi-input and multi-clock maintenance obstruction type JK trigger. The JK trigger comprises a multi-input basic RS latch, two or more than two input units and JK conversion circuits; two output ends of the multi-input basic latch are q and nq respectively; the num...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The present invention discloses a multi-input and multi-clock maintenance obstruction type JK trigger. The JK trigger comprises a multi-input basic RS latch, two or more than two input units and JK conversion circuits; two output ends of the multi-input basic latch are q and nq respectively; the number of the input units is the same as that of the JK conversion circuits; two output ends of any input unit are respectively connected with an input end of the multi-input basic latch to form a maintenance obstruction type D trigger; each input unit comprises a data input and a clock trigger end; the data input end of the input unit is connected with an output end of each JK conversion circuit; and each JK conversion circuit comprises two data input ends. The trigger can be used as a common memory and applied to the design of a sequential circuit, especially to the design of a distributed system driven by events or an asynchronous circuit, compared with the prior trigger, the trigger is directly driven by events un |
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