High-performance digitized gain fine adjustment circuit

The utility model discloses a high-performance digitized gain fine adjustment circuit characterized in that: an analog signal port of a digital/analog conversion chip packaging a R-2R ladder-shaped resistor network is connected with an analog operational amplifier, a data port of the digital/analog conversion chip packaging the R-2R ladder-shaped resistor network is connected with a microprocessor through an IO-to-IIC circuit, and a command port of the digital/analog conversion chip packaging the R-2R ladder-shaped resistor network is connected with the microprocessor. The high-performance digitized gain fine adjustment circuit of the utility model has the beneficial effects that: a gain resolution of the gain fine adjustment circuit can reach 14 digits; the R-2R ladder-shaped resistor network with uniform height can make the gain fine adjustment circuit have a high linearity; wiring and layout of the R-2R ladder-shaped resistor network in the gain fine adjustment circuit are fixed, thus the gain fine adjustm