SOI N-type integrated high-current combined semi-conductor device

The utility model provides an SOI (silicon-on-insulator) N-type integrated high-current semi-conductor combination device which can improve the current density. The combined semi-conductor device comprises a P-type substrate and a buried oxide layer arranged on the P-type substrate, wherein, a P-type epilayer is arranged on the buried oxide layer and is divided into an area I and an area II; the area I comprises an N-type drift region, a P-type deep pit, an N-type buffering pit, a P-type leakage region, an N-type source region and a P-type body contact region, a field oxide layer and a gate oxide layer are arranged on the silicon surface, and a polysilicon gate is arranged on the gate oxide layer; and the area II comprises an N-type triode drift region, another P-type pit, an N-type triode buffering pit, a P-type emission region, an N-type base region, another N-type source region and another P-type body contact region, another field oxide layer and another gate oxide layer are arranged on the silicon surface